Lateral/vertical semiconductor device with embedded isolator

A lateral/vertical field effect transistor comprising:

• a heterostructure including a device channel adjacent to a first surface of the device structure, wherein the device channel includes a lateral portion, a vertical portion, and a transition region between the lateral portion and the vertical portion;
• a first contact to the lateral portion of the device channel located on the first surface;
• a second contact to the vertical portion of the device channel, wherein the second contact is located on an opposing surface of the device structure as the first surface;
• a set of insulating layers having a resistivity above 1010 Ohm×cm and located in the device structure between the lateral portion of the device channel and the second contact, wherein an opening in the set of insulating layers defines the transition region of the device channel;
• and
• a channel layer located between the set of insulating layers and the second contact, and within the opening in the set of insulating layers.

A lateral/vertical device comprising:

• a device structure including a lateral portion of a device channel located adjacent to a first surface of the device structure, wherein the device structure includes a set of insulating layers having a resistivity above 1010 Ohm×cm and located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface, and wherein an opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel;
• a first contact to the lateral portion of the device channel on the first surface;
• a second contact to the vertical portion of the device channel on the second surface;
• and
• a channel layer located between the set of insulating layers and the second contact, and within the opening in the set of insulating layers.