High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

A method of forming a multilayer structure, the method comprising:

• forming a crystalline semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the crystalline semiconductor nitride layer is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the crystalline semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
• forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the crystalline semiconductor nitride layer;
• and
• bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.