Fin cut etch process for vertical transistor devices

A method for fabricating a semiconductor device including a vertical transistor, comprising:

• forming a fin structure from a substrate, the fin structure including a fin and a cap layer disposed on the fin;
• forming a bottom source/drain region on the substrate adjacent to the fin, wherein the cap layer protects sidewalls of the fin during the formation of the bottom source/drain region;
• forming a first dielectric fill on the substrate after defining an active diffusion cut region;
• etching a longitudinal end portion of the fin to create a gap exposing the substrate;
• filling the gap with a second dielectric fill;
• forming a gate and a top source/drain region;
• and
• forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

A semiconductor device including a vertical transistor, comprising:

• a substrate;
• a fin disposed on the substrate;
• a bottom source/drain region disposed on the substrate adjacent to the fin;
• a bottom spacer disposed on the bottom source/drain region;
• a gate stack adjacent to the fin disposed on the bottom spacer;
• a top spacer disposed on the gate stack;
• a top source/drain region disposed on the top spacer and the fin;
• and
• a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region.