US 10,483,370 B2Granted

Semiconductor structure with unleveled gate structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChai-Wei Chang, Che-Cheng Chang, Po-Chi Wu, Yi-Cheng Chao

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Abstract

Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over a portion of the gate dielectric layer. The gate structure further includes a gate electrode layer formed over a portion of the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

Claims20

Dependent claims

A semiconductor structure, comprising:

a fin structure formed over a substrate;
a gate structure formed across the fin structure, wherein the gate structure comprises:
a gate dielectric layer formed over the substrate;
a work function metal layer formed over a portion of the gate dielectric layer;
and
a gate electrode layer formed over a portion of the work function metal layer,
wherein a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer;
a spacer formed on a sidewall of the gate structure;
and
a dielectric material formed over the top surface of the gate electrode layer and in direct contact with the top surface of the gate electrode layer,
wherein a topmost surface of the spacer is higher than a topmost surface of the gate electrode layer, and a bottommost of the dielectric material is lower than a topmost surface of the gate dielectric layer.

8 more elements

A semiconductor structure, comprising:

a fin structure formed over a substrate;
a gate structure formed across the fin structure, wherein the gate structure comprises:
a gate dielectric layer formed over the substrate;
a work function metal layer formed over the gate dielectric layer;
and
a gate electrode layer formed over the work function metal layer;
a spacer formed over a sidewall of the gate structure;
and
a hard mask structure formed over the gate structure, wherein the hard mask structure comprises a first portion formed directly above the work function metal layer, a second portion formed directly above the gate dielectric layer, and a third portion formed directly above the gate electrode layer, a distance between a top surface of the first portion of the hard mask structure and a top surface of the work function metal layer is greater than a distance between a top surface of the second portion of the hard mask structure and a top surface of the gate dielectric layer, and the distance between the top surface of the second portion of the hard mask structure and the top surface of the gate dielectric layer is greater than a distance between a top surface of the third portion of the hard mask structure and a top surface of the gate electrode layer, and the hard mask structure is made of a dielectric material,
wherein each of the first portion, the second portion, and the third portion extends from a bottom surface to a too surface of the hard mask structure,
wherein a topmost surface of the hard mask structure is flush with a topmost surface of the spacer.

8 more elements

A semiconductor structure, comprising:

a fin structure formed over a substrate;
a gate structure formed across the fin structure, wherein the gate structure comprises:
a gate dielectric layer formed over the substrate;
a first work function metal layer formed over the gate dielectric layer;
and
a gate electrode layer formed over the first work function metal layer;
a spacer formed on a sidewall of the gate dielectric layer;
and
a dielectric structure having a first portion, a second portion, and a third portion formed over the gate structure, wherein the first portion is located between the second portion and the third portion, and the second portion is in direct contact with the spacer, and a bottom surface of the first portion is lower than a bottom surface of the second portion and the bottom surface of the second portion is lower than a bottom surface of the third portion, and the first portion, the second portion, and the third portion of the dielectric structure are made of a same material,
wherein each of the first portion, the second portion, and the third portion extends from a bottom surface to a too surface of the hard mask structure,
wherein a topmost surface of the spacer is higher than the bottom surface of the second portion and the bottom surface of the third portion.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/807,860Filed 9 Nov 2017 · division
Priority: 15 May 2015
Published: US 2018/0069095 A18 Mar 2018
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers

Family

Application14/713,517Parent of this division · filed 15 May 2015
US 2018/0069095 A1Pre-grant publication · published 8 Mar 2018
US 9,818,841 B2Parent of this division
US 2016/0336426 A1Published application
US 10,483,370 B2This patent

From the US filing history. Foreign family members aren’t listed.

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