US 10,483,356 B2Granted

Power semiconductor device with optimized field-plate design

AssigneeSiliconix Incorporated

InventorsMax Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso

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Abstract

A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.

Claims10

Dependent claims

A semiconductor device comprising:

a source bonding pad;
a drain bonding pad;
a drain metallization structure comprising a drain field plate;
and
a source metallization structure comprising a source field plate;
at least a portion of the source bonding pad being situated directly over an active area of the device in a first area of the device;
at least a portion of the drain bonding pad being situated directly over an active area of the device in a second area of the device;
wherein the source field plate has a first dimension positioned in the first area, and a second dimension different from the first dimension positioned in an area of the device other than the first area;
and
wherein the drain field plate has a first dimension positioned in the second area, and a second dimension different from the first dimension positioned in an area of the device other than the second area.

7 more elements

A method of making a semiconductor device comprising:

forming a source bonding pad;
forming a drain bonding pad;
forming a drain metallization structure comprising a drain field plate;
forming a source metallization structure comprising a source field plate;
situating at least a portion of the source bonding pad directly over an active area of the device in a first area of the device;
situating at least a portion of the drain bonding pad directly over an active area of the device in a first area of the device;
and
positioning a portion of the source field plate having a first dimension in the first area, and positioning a portion of the source field plate having a second dimension different from the first dimension in an area of the device other than the first area;
and
positioning a portion of the drain field plate having a first dimension in the second area, and positioning a portion of the drain field plate having a second dimension different from the first dimension in an area of the device other than the second area.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/906,698Filed 27 Feb 2018
Published: US 2019/0267456 A129 Aug 2019
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 30/475
High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]: having wider bandgap layer formed on top of lower bandgap…
H10D 64/112
Field plates: comprising multiple field plate segments
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10D 30/4755
Having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs: having wide bandgap…

Family

US 2019/0267456 A1Pre-grant publication · published 29 Aug 2019
US 10,483,356 B2This patent

From the US filing history. Foreign family members aren’t listed.

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