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US 10,483,324 B2Granted
3D vertical memory array cell structures and processes
OwnerFu-Chang Hsuinventor
Life of this patent
Estimating the term…
Abstract
Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a cell structure includes a word line, a selector layer, and a memory layer. The word line, the selector layer, and the memory layer form a vertical cell structure in which at least one of the selector layer and the memory layer are segmented to form a segment that blocks sneak path leakage current on the word line.
Claims6
A method for forming a vertical memory structure, comprising:
- forming a layer stack comprising word line layers separated by insulator layers;
- forming an opening through the layer stack to expose internal surfaces of the word line layers;
- depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
- depositing a memory material directly on the selector material;
- and
- depositing bit line material directly on the memory material.
3 more elements
A 3D vertical array that includes a plurality of cell structures that block sneak path leakage current, the cell structures formed by performing the operations of:
- forming a layer stack comprising word line layers separated by insulator layers;
- forming an opening through the layer stack to expose internal surfaces of the word line layers;
- depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
- depositing a memory material directly on the selector material;
- and
- depositing bit line material directly on the memory material.
3 more elements
Dependencies are inferred from the claim text.