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US 10,483,321 B2Granted
High density memory architecture using back side metal layers
AssigneeIntel Corporation
InventorsYih Wang, Patrick Morrow
Life of this patent
Estimating the term…
Abstract
A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.
Claims16
A microelectronic memory comprising:
- a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
- a source line directly contacting the substrate back surface;
- and
- a memory bitcell transistor on the substrate front surface.
1 more element
A microelectronic memory comprising:
- a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
- a word line on the substrate back surface;
- a source line positioned between the word line and the substrate;
- and
- a memory bitcell transistor on the substrate front surface.
2 more elements
Dependencies are inferred from the claim text.