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US 10,483,313 B2Granted
Solid-state image sensor and electronic device
AssigneeSony Corporation
InventorToshifumi Wakano
Life of this patent
Estimating the term…
Abstract
There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.
Claims20
An imaging device comprising:
- a first chip and a second chip stacked to the first chip, wherein the second chip includes, a plurality of 8-pixel share units, wherein each 8-pixel share unit of the plurality of 8-pixel share units includes:
- first to fourth photodiode regions sharing a first floating diffusion and fifth to eighth photodiode regions sharing a second floating diffusion, the first to eighth photodiode regions sharing a single amplification transistor and a reset transistor;
- and
- a power supply line for supplying a drain of the reset transistor with a power supply voltage, the power supply line including a first line disposed on a first layer and extending along a first direction and a second line disposed on a second layer and extending along a second direction, the first and second lines being coupled to each other and pass through the 8-pixel share unit.
1 more element
An electronic apparatus, comprising:
- an imaging device comprising:
- a first chip and a second chip stacked to the first chip, the second chip having a first side as a light-incident side and a second side bonded to the first chip, wherein the second chip includes, a plurality of 8-pixel share units, wherein each 8-pixel share unit of the plurality of 8-pixel share units includes:
- first to fourth photodiode regions sharing a first floating diffusion and fifth to eighth photodiode regions sharing a second floating diffusion, the first to eighth photodiode regions sharing a single amplification transistor and a reset transistor;
- and
- a power supply line for supplying a drain of the reset transistor with a power supply voltage, the power supply line including a first line disposed on a first layer and extending along a first direction and a second line disposed on a second layer and extending along a second direction, the first and second lines being coupled to each other and pass through the 8-pixel share unit.
2 more elements
Dependencies are inferred from the claim text.