Array substrate and display panel

An array substrate, comprising:

• a plurality of signal lines;
• a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality of secondary discharging lines being arranged to cross the plurality of signal lines;
• a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines and arranged at an identical side of an entirety of the plurality of secondary discharging lines;
• and
• a primary discharging line connected to the plurality of secondary discharging lines,
• wherein a first end of each of the plurality of first electrostatic discharging units is connected to a corresponding signal line of the plurality of signal lines, and a second end of the each of the plurality of first electrostatic discharging units is connected to one of the plurality of secondary discharging lines,
• each first electrostatic discharging unit of the plurality of first electrostatic discharging units comprises a first thin film transistor (TFT), a second TFT, and a third TFT;
• a gate electrode and a source electrode of the first TFT are short-circuited and connected to one of the plurality of signal lines corresponding to the each first electrostatic discharging unit, and a drain electrode of the first TFT is connected to a source electrode of the second TFT and a gate electrode of the third TFT;
• a gate electrode and a drain electrode of the second TFT are short-circuited and connected to the one of the plurality secondary discharging lines corresponding to the each first electrostatic discharging unit;
• a source electrode of the third TFT is directly connected to the one of the plurality of signal lines, and a drain electrode of the third TFT is directly connected to the one of the plurality of secondary discharging lines;
• and
• an extension portion of the one of the plurality of signal line corresponding to the each first electrostatic discharging unit is formed into the source electrode of the first TFT and the source electrode of the third TFT, the source electrode of the first TFT is connected to the gate electrode of the first TFT through a first via-hole, an active region of the first TFT is formed above the gate electrode of the first TFT, and the source electrode and the drain electrode of the first TFT are in direct contact with the active region of the first TFT so as to form a source region and a drain region of the first TFT.