US 10,483,287 B1Granted

Double gate, flexible thin-film transistor (TFT) complementary metal-oxide semiconductor (MOS) (CMOS) circuits and related fabrication methods

AssigneeQUALCOMM Incorporated

InventorsXia Li, Bin Yang, Gengming Tao

Life of this patent

Estimating the term…

Loading patent…

Abstract

Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.

Claims15

Dependent claims

A complementary metal-oxide semiconductor (CMOS) circuit, comprising:

a flexible substrate;
at least one P-type Field-Effect Transistor (FET) (PFET) formed on a first surface of the flexible substrate, each of the at least one PFET comprising:
a first gate disposed on the first surface of the flexible substrate;
a P-type thin-film semiconductor structure disposed over the first gate in a first axis direction, the P-type thin-film semiconductor structure comprising a first source/drain region, a second source/drain region, and a first channel region between the first and second source/drain regions;
and
a second gate disposed over the P-type thin-film semiconductor structure in the first axis direction opposite to the first gate;
at least one N-type FET (NFET) formed on the first surface of the flexible substrate, each of the at least one NFET comprising:
a third gate disposed on the first surface of the flexible substrate;
an N-type thin-film semiconductor structure disposed over the third gate in the first axis direction, the N-type thin-film semiconductor structure comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third and fourth source/drain regions;
and
a fourth gate disposed over the N-type thin-film semiconductor structure in the first axis direction opposite to the third gate;
and
at least one metal contact electrically coupling the second source/drain region of the at least one PFET and the third source/drain region of the at least one NFET.

10 more elements

A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit on a flexible substrate, comprising:

forming a first gate and a second gate on a surface of the flexible substrate;
forming a P-type semiconductor structure over the first gate in a first axis direction;
forming an N-type semiconductor structure over the second gate in the first axis direction;
forming first and second P-type Field-Effect Transistor (FET) (PFET) source/drain regions in first and second end portions, respectively, of the P-type semiconductor structure;
forming third and fourth N-type FET (NFET) source/drain regions in first and second end portions, respectively, of the N-type semiconductor structure;
forming a first metal contact on the second PFET source/drain region and a second metal contact on the third NFET source/drain region, electrically coupling the second PFET source/drain region and the third NFET source/drain region through the first metal contact and the second metal contact;
forming a third gate over the P-type semiconductor structure opposite to the first gate in the first axis direction;
and
forming a fourth gate over the N-type semiconductor structure opposite to the second gate in the first axis direction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/138,084Filed 21 Sep 2018
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 86/411
Characterised by multiple TFTs: characterised by materials, geometry or structure of the substrates
H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D 30/6733
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: multi-gate TFTs
H10D 30/6734
Multi-gate TFTs: having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs

Family

No related US applications are recorded in the indexed filing history.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key