Logic semiconductor device

A semiconductor device comprising:

• a plurality of stacked transistors,
• wherein:
• the plurality of stacked transistors comprise:
• a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;
• a gate electrode disposed to cover the intrinsic region;
• and
• a gate insulating layer disposed between the gate electrode and the intrinsic region,
• wherein not all of the plurality of stacked transistors have a same first conductive type,
• wherein:
• the plurality of stacked transistors include a pair of first transistors disposed at a lower layer and a pair of second transistors disposed at an upper layer, and
• the first transistor and the second transistor constitute a NOR logic circuit or a NAND logic circuit.

A semiconductor device comprising:

• a plurality of stacked transistors,
• wherein:
• each of the transistors comprises:
• a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;
• a gate electrode disposed to cover the intrinsic region;
• and
• a gate insulating layer disposed between the gate electrode and the intrinsic region,
• wherein not all of the plurality of stacked transistors have a same first conductive type,
• wherein:
• the plurality of stacked transistors include an n-channel semiconductor device in which the first conductivity type of the semiconductor column is n-type and a p-channel semiconductor device in which the first conductivity type of the semiconductor column is p-type, respectively, and
• the plurality of stacked transistors is configured to perform at least one of inverter, NAND, and NOR logic operations.