Semiconductor memory device

A method of manufacturing a semiconductor memory device comprising:

• forming a stacked structure on a substrate, wherein the stacked structure includes word lines stacked on a cell array region a substrate and cell plugs, wherein the substrate includes the cell array region, a word line contact region and a page buffer region;
• forming first contact plugs coupled to the cell plugs in the cell array region;
• forming second contact plugs coupled to transistors in the page buffer region;
• and
• forming bit lines coupling the first contact plugs and the second plugs so that the page buffer region is coupled to the cell array region through the bit lines,
• wherein one of the first contact plugs is shifted to the word line contact region with respect to a corresponding second contact plug and a distance by which the one of the first contact plugs is shifted with respect to the corresponding second contact plug is greater than a distance by which another first contact plug is shifted with respect to a corresponding second contact plug.

A method of manufacturing a semiconductor memory device comprising:

• forming a stacked structure on a substrate, wherein the stacked structure includes cell plugs extending from a substrate and conductive layers surrounding the cell plugs and extending in a first direction;
• and
• forming bit lines coupled to the cell plugs and extending in a second direction crossing the first direction,
• wherein the bit lines include a first bit line and a second bit line adjacent to each other in the first direction, and
• wherein the second bit line has a curved structure in the first direction and a curvedness of the second bit line is greater than a curvedness of the first bit line.

A method of manufacturing a semiconductor memory device comprising:

• forming an insulating layer over a substrate, wherein the substrate includes a cell array region and a page buffer region;
• forming a plurality of mask patterns over the insulating layer at the cell array region and the page buffer region;
• forming a plurality of spacer pairs on respective sidewalls of the mask patterns;
• removing the mask patterns;
• forming trenches in the insulating layer by etching the insulating layer using the spacer pairs as an etch barrier;
• and
• forming the bit lines in the trenches, respectively,
• wherein at least one of the mask patterns has a greater width in the cell array region than in the page buffer region,
• wherein at least one of the spacer pairs has a greater distance in the cell array region than in the page buffer region, and
• wherein the bit lines include a first bit line and a second bit line, the second bit line has a curved structure and a curvedness of the second bit line is greater than a curvedness of the first bit line.