Semiconductor device including memory cell array with transistors disposed in different active regions

A semiconductor device comprising:

• a first conductivity type first MIS transistor electrically connected between a first node with which a first potential is supplied and a second node;
• a second conductivity type first MIS transistor electrically connected between the second node and a third node with which a second potential different from the first potential is supplied;
• a second conductivity type second MIS transistor electrically connected between the second node and the third node in parallel with the second conductivity type first MIS transistor;
• a first conductivity type second MIS transistor electrically connected between the first node and a fourth node;
• a second conductivity type third MIS transistor electrically connected between the third node and the fourth node;
• a second conductivity type fourth MIS transistor electrically connected between the third node and the fourth node in parallel with the second conductivity type third MIS transistor;
• a second conductivity fifth MIS transistor electrically connected between the second node and a fifth node;
• a second conductivity type sixth MIS transistor electrically connected between the fourth node and a sixth node;
• a first conductivity type first well region;
• a first conductivity type second well region;
• and
• a second conductivity type well region arranged between the first conductivity type first well region and the first conductivity type second well region,
• wherein the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are arranged in a first active region,
• wherein the second conductivity type second MIS transistor is arranged in a second active region which is separated from the first active region, and which is arranged next to the first active region,
• wherein the second conductivity type third MIS transistor is arranged in a third active region,
• wherein the second conductivity type fourth MIS transistor and the second conductivity type sixth MIS transistor are arranged in a fourth active region which is separated from the third active region, and which is arranged next to the third active region,
• wherein the first, second, third and fourth active regions are arranged in a first direction, and arranged in sequence, and separated from one another,
• wherein, in plan view, the first active region and the second active region are arranged in the first conductivity type first well region,
• wherein, in plan view, the third active region and the fourth active region are arranged in the first conductivity type second well region,
• wherein a gate electrode of the second conductivity type fifth MIS transistor is comprised of a first part of a first gate wiring which is extended in the first direction, and which is arranged over the first active region,
• wherein a gate electrode of the second conductivity type first MIS transistor is comprised of a second part of a second gate wiring which is extended in the first direction, and which is arranged over the first active region and the second active region,
• wherein a gate electrode of the second conductivity type second MIS transistor is comprised of a third part of the second gate wiring,
• wherein a gate electrode of the second conductivity type third MIS transistor is comprised of a fourth part of a third gate wiring which is extended in the first direction, and which is arranged over the third active region and the fourth active region,
• wherein a gate electrode of the second conductivity type fourth MIS transistor is comprised of a fifth part of the third gate wiring,
• wherein a gate electrode of the second conductivity type sixth MIS transistor is comprised of a sixth part of a fourth gate wiring which is extended in the first direction, and which is arranged over the fourth active region,
• wherein a length of the first active region in a second direction crossing to the first direction is longer than a length of the second active region in the second direction, and
• wherein a length of the fourth active region in the second direction is longer than a length of the third active region in the second direction.