Eight-transistor static random-access memory, layout thereof, and method for manufacturing the same

A Static Random Access Memory (SRAM) cell, comprising:

• a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter;
• and
• a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each other, gate electrodes of the read pull-down transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,
• wherein a first doping concentration of impurities doped in a channel region of the second pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and are not doped in the channel region of the first pull-down transistor.

A semiconductor device, comprising:

• first and second transistors arranged along a first direction in an order of the first transistor and the second transistor on a first path;
• third through fifth transistors sequentially arranged along the first direction on a second path, the second path being spaced apart from the first path in a second direction perpendicular to the first direction;
• a first gate electrode layer continuously extending from a first end thereof to a second end thereof along the first direction, and covering channel regions of the first and second transistors;
• and
• a second gate electrode layer continuously extending from a third end thereof to a fourth end thereof along the first direction, and covering at least channel regions of the third and fourth transistors, gate electrodes of the third through fifth transistors being electrically connected to each other, and the gate electrodes of the third and fourth transistors constituting a portion or an entirety of the second gate electrode layer, wherein:
• the second end of the first gate electrode layer and the third end of the second gate electrode layer are point symmetric with respect to a geometric center of the first through fourth transistors, and
• a first doping concentration of a second type impurity doped in the channel regions of the fourth and fifth transistors is greater than a second doping concentration of the second type impurity doped in the channel region of the first transistor, or the second type impurity is doped in the channel regions of the fourth and fifth transistors and is not doped in the channel region of the first transistor.