Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection

A method comprising:

• providing an electrostatic discharge (ESD) protection structure in an integrated circuit, wherein the ESD protection structure comprises:
• a first semiconductor region of a first conductivity type in which is formed a shallow collector contact region of a second conductivity type that is opposite the first conductivity type, where the first semiconductor region of the first conductivity type is formed with a first doping level to overlay an epitaxial semiconductor layer of the first conductivity type and a second lower doping level, where the epitaxial semiconductor layer is formed over a semiconductor substrate of the first conductivity type having third doping level which is lower than the first and second doping levels;
• a shallow emitter contact region of the second conductivity type located next to and spaced apart from the shallow collector contact region;
• a shallow base contact region of first conductivity type located next to and spaced apart from the shallow emitter contact region;
• and
• a collector halo extension region and emitter halo extension region extending below at least the shallow collector and emitter contact regions, respectively, where the shallow emitter and base contact regions are directly connected to emitter and base contact terminals of a first grounded terminal and where the shallow collector contact region is connected to a collector contact terminal of a second terminal;
• and
• applying a positive voltage between the second terminal and the first grounded terminal of the integrated circuit.

A method of fabricating a semiconductor device comprising:

• forming, in a semiconductor substrate of a first conductivity type and having a first doping level, an uppermost first region of semiconductor material having the first conductivity type over a buried well region of a second, opposite conductivity type by:
• forming an epitaxial semiconductor layer of the first conductivity type and a second higher doping level than the first doping level overlying the buried well region;
• and
• forming the uppermost first region of semiconductor material of the first conductivity type and a third higher doping level than the second doping level over the epitaxial semiconductor layer;
• forming one or more shallow trench isolation structures on an upper surface of the uppermost first region of semiconductor material to define an outer base contact location and a plurality of alternating collector and emitter contact locations in a multi-finger arrangement in the semiconductor substrate;
• forming collector and emitter contact regions of a second conductivity type in the plurality of alternating collector and emitter contact locations;
• forming a base contact region of the first conductivity type in the outer base contact location;
• and
• forming separate collector halo extension regions and emitter halo extension regions to surround and enclose at least the collector and emitter contact regions;
• and
• forming first and second terminals such that the first terminal comprises emitter and base contact terminals in electrical contact with the emitter and base contact region regions and the second terminal comprises a collector contact terminal in electrical contact with the collector contact region, thereby forming a single polarity electrostatic discharge (ESD) clamp coupled between the first and second terminals.