US 10,483,255 B2Granted

Semiconductor device

AssigneeSocionext Inc.

InventorsHirotaka Takeno, Atsushi Okamoto

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Abstract

A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

Claims10

Dependent claims

A semiconductor device, comprising:

a substrate;
a first circuit;
a first power supply line;
a second power supply line which is electrically coupled to the first circuit;
a first ground line which is electrically coupled to the first circuit;
a first switch circuit which includes a first switch section;
a first well tap which is electrically coupled to the substrate and the second power supply line;
a second circuit;
a third power supply line;
a fourth power supply line which is electrically coupled to the second circuit;
a second ground line which is electrically coupled to the second circuit;
and
a second switch circuit which includes a second switch section,
wherein
the first switch section is adjacent to the first well tap in a plan view,
the first switch section includes a first switch transistor which is disposed between the first power supply line and the second power supply line,
the second switch section is adjacent to no well tap in a plan view,
the second switch section includes a second switch transistor which is disposed between the third power supply line and the fourth power supply line.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/448,241Filed 21 Jun 2019 · division
Priority: JP 2017-08940728 Apr 2017
Published: US 2019/0312024 A110 Oct 2019
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H03K 17/161
Modifications for eliminating interference voltages or currents: in field-effect transistor switches
H03K 19/0016
Arrangements for reducing power consumption: by using a control or a clock signal, e.g. in order to apply power supply
H10D 62/151
Source or drain regions of field-effect devices: of igfets

Family

Application15/953,899Parent of this division · filed 16 Apr 2018
US 2019/0312024 A1Pre-grant publication · published 10 Oct 2019
US 10,373,943 B2Parent of this division
US 2018/0315743 A1Published application
US 10,483,255 B2This patent

From the US filing history. Foreign family members aren’t listed.

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