Stacked electronic device and method for fabricating the same

A method for fabricating a stacked electronic device, comprising:

• providing a first substrate, wherein the first substrate comprises a wafer, a chip, or a combination thereof;
• performing a first three-dimensional (3D) printing to form a first insulating layer and a plurality of first redistribution layers (RDLs) on the first substrate, wherein the plurality of first RDLs is embedded in the first insulating layer and is electrically connected to contacts of the first substrate;
• performing a second 3D printing to form a second substrate, a plurality of through-substrate vias (TSVs) and insulating spacers on the first insulating layer simultaneously and respectively by at least three print heads, wherein the plurality of TSVs pass through the second substrate and are electrically connected to the plurality of first RDLs, and the insulating spacers electrically isolate the second substrate from the plurality of TSVs;
• performing a third 3D printing to form a second insulating layer and a plurality of second RDLs on the second substrate, wherein the plurality of second RDLs is embedded in the second insulating layer and electrically connected to the plurality of TSVs;
• and
• bonding a plurality of contacts of a third substrate to the plurality of second RDLs, so that the third substrate is mounted onto the second insulating layer.