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US 10,483,224 B2Granted
Semiconductor chip
AssigneeSamsung Electronics Co., Ltd.
InventorsJeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
Life of this patent
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Abstract
A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
Claims20
A semiconductor chip comprising:
- a semiconductor substrate including a bump region, a non-bump region, and a dummy region between the bump region and the non-bump region;
- a dummy pattern on the dummy region;
- a bump on the bump region, the non-bump region having no bump;
- and
- a passivation layer on the bump region, the dummy region, and the non-bump region of the semiconductor substrate,
- a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region,
- the passivation layer covering the dummy pattern and insulating the dummy pattern, and
- the passivation layer including a step between the bump region and the non-bump region, the step defined by an upper surface of the passivation layer at a portion of the passivation layer that protrudes upward over a boundary between the dummy region and the non-bump region.
5 more elements
A semiconductor chip comprising:
- a semiconductor substrate including a first surface opposite a second surface,
- the semiconductor substrate including a bump region, a non-bump region, a redistribution wiring region, and a dummy region;
- a bump pad on the first surface of the semiconductor substrate in the bump region;
- a bump on the bump pad, the non-bump region having no bump;
- at least one of a redistribution wiring pattern on the redistribution wiring region and a dummy pattern on the dummy region, the at least one of the redistribution wiring pattern and the dummy pattern being on the first surface or the second surface of the semiconductor substrate;
- and
- a passivation layer covering the bump region, the non-bump region, the redistribution wiring region, and the dummy region on the first surface or the second surface of the semiconductor substrate,
- a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region, and
- the passivation layer including a first step between the bump region and the non-bump region, the first step defined by an upper surface of the passivation layer at a portion that protrudes upward over a boundary between the dummy region and the non-bump region.
6 more elements
A semiconductor chip comprising:
- a semiconductor substrate including a first surface opposite a second surface;
- a bump connected to one of the first surface and the second surface;
- a redistribution pattern on the semiconductor substrate, the redistribution pattern being spaced apart from the bump;
- and
- a passivation layer on the semiconductor substrate and extending along the one of the first surface and the second surface of the semiconductor substrate,
- the passivation layer including a first portion having a first thickness, a second portion having a second thickness that is less than the first thickness, and a step defining the first portion and the second portion,
- the first portion of the passivation layer covering the redistribution pattern,
- the step defined by an upper surface of the passivation layer at a portion that protrudes upward,
- the first portion of the passivation layer extending along an upper surface and a side surface of the redistribution pattern, and
- the first portion of the passivation layer defining a hole between the bump and the semiconductor substrate.
7 more elements
Dependencies are inferred from the claim text.