Array substrate with static charge releasing pattern and method for producing the same

A method for manufacturing an array substrate, comprising a step of forming a metal pattern and an electrically conductive pattern on a base substrate sequentially, wherein in a patterning process of forming the electrically conductive pattern, a static charge releasing pattern insulated from the electrically conductive pattern and electrically connected to the metal pattern is also formed, the static charge releasing pattern being formed in a same layer as the electrically conductive pattern and formed by the same material as the electrically conductive pattern,

• wherein the metal pattern is a signal line, the signal line being continuous and comprising an input end and an output end, and the static charge releasing pattern comprises:
• a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the signal line;
• and
• a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the signal line.

A method of manufacturing an array substrate, comprising:

• forming a gate line and a gate insulation layer sequentially;
• forming one or more first via holes in the gate insulation layer;
• forming a source-drain metal pattern and a first portion of a static charge releasing pattern in a same layer and of a same material by means of a single patterning process, the first portion of the static charge releasing pattern being electrically connected to the gate line through the first via hole formed in the gate insulation layer;
• depositing a passivation layer;
• forming one or more second via holes in the passivation layer;
• and
• forming a transparent electrode and a second portion of the static charge releasing pattern in a same layer and of a same material by means of a single patterning process, the second portion of the static charge releasing pattern being electrically connected to the first portion of the static charge releasing pattern through the second via hole formed in the passivation layer,
• wherein the gate line is continuous and comprises an input end and an output end,
• wherein the static charge releasing pattern comprises:
• a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the gate line;
• and
• a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the gate line.