Power module and fabrication method for the same

A power module comprising:

• a substrate;
• a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
• a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed;
• and
• a leadframe bonded to an upper surface of the semiconductor device, wherein
• the leadframe is divided into a plurality of leadframes, wherein
• the leadframe divided into the plurality of frames comprises:
• a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
• a second leadframe electrically insulated from the first leadframe, the power module further comprising:
• a third leadframe electrically connected to the first leadframe, the third leadframe being disposed on the first signal electrode pattern;
• and
• a fourth leadframe electrically connected to the second leadframe, the fourth leadframe being disposed on the second signal electrode pattern.

A power module comprising:

• a substrate;
• a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
• a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed;
• a leadframe bonded to an upper surface of the semiconductor device;
• a first soldering layer disposed on the first pad electrode;
• a stress relaxation layer disposed on the first soldering layer, the stress relaxation layer configured to relax a stress applied to the first soldering layer;
• and
• a second soldering layer disposed on the stress relaxation layer,
• wherein
• the leadframe is divided into a plurality of leadframes, wherein
• the leadframe divided into the plurality of frames comprises:
• a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
• a second leadframe electrically insulated from the first leadframe, wherein
• the semiconductor comprises a first pad electrode and a second pad electrode at a front surface side, wherein
• the first leadframe is bonded to the first electrode pattern and the first pad electrode,
• the second leadframe is bonded to the second pad electrode, and
• the first leadframe is connected to the first pad electrode via the stress relaxation layer.