Interconnection structure, fabricating method thereof, and semiconductor device using the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
Life of this patent
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Abstract
A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
Claims20
A device comprising:
- a multi-gate transistor, the multi-gate transistor including an epitaxial source/drain region;
- a dielectric layer overlying the epitaxial source/drain region;
- a contact extending through an opening in the dielectric layer and electrically contacting the epitaxial source/drain region, the contact including:
- a silicide layer contacting the epitaxial source/drain region, wherein a Si concentration of the silicide is varied along a height of the silicide;
- a barrier layer contacting the silicide layer;
- a metal layer contacting the barrier layer and contacting sidewalls of the opening in the dielectric layer, wherein the silicide layer is a silicide of the epitaxial source/drain region and the metal layer;
- and
- a conductor contacting the barrier layer, wherein the barrier layer extends between and separates the conductor and the silicide layer.
A device comprising:
- a channel region;
- a gate conductor wrapped around the channel region;
- a source/drain region on one side of the channel region;
- a dielectric layer over the source/drain region, the dielectric layer having an opening therein aligned to the source/drain region;
- a portion of the source/drain region forming a silicide layer in the opening;
- a metal layer lining sidewalls of the opening, wherein the silicide is a silicide of the source/drain region and the metal layer, and further wherein a silicon concentration of the silicide varies from a top of the silicide layer to a bottom of the silicide layer;
- a barrier layer on the metal layer;
- and
- a conductor on the barrier layer and filling the opening.
A method comprising:
- forming a multi-gate transistor structure on a substrate;
- covering the multi-gate transistor structure with a dielectric layer;
- forming an opening in the dielectric layer, the opening exposing a source/drain region of the multi-gate transistor structure, wherein forming an opening removes a top portion of the source/drain;
- lining the opening with a metal layer;
- lining the metal layer with a barrier layer;
- annealing the source/drain region and the metal layer to form a silicide;
- and
- forming a conductor material atop the silicide and the barrier.
Dependencies are inferred from the claim text.