Logic cell structure with interconnection design and configuration

A semiconductor structure, comprising:

• a semiconductor substrate;
• a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
• a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
• a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction;
• and
• a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
• the first metal lines have a first pitch P1;
• the second metal lines have a second pitch P2;
• the third metal lines have a third pitch P3;
• the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2;
• the FETs include an n-type conductivity field-effect transistor (nFET) and a p-type conductivity field-effect transistor (pFET) coupled together through a common drain to form an inverter, and
• the inverter spans a dimension of about 2*P4 along the second direction.

A semiconductor structure, comprising:

• a semiconductor substrate;
• a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
• a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
• a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction;
• and
• a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
• the first metal lines have a first pitch P1;
• the second metal lines have a second pitch P2;
• the third metal lines have a third pitch P3;
• the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2;
• the FETs are coupled to a logic gate being one of an NAND gate and an NOR logic gate;
• and
• the logic gate spans a dimension of about 3*P4 along the second direction.