US 10,483,200 B1Granted

Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance

AssigneeQUALCOMM Incorporated

InventorsHaining Yang, Xiangdong Chen, John Jianhong Zhu

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Abstract

Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.

Claims24

Dependent claims

An integrated circuit (IC), comprising:

a substrate;
a diffusion region disposed in the substrate, the diffusion region comprising a semiconductor channel each having a first longitudinal axis in a first direction;
a dummy gate extending along a second longitudinal axis orthogonal to the first longitudinal axis, the first dummy gate disposed above the diffusion region;
a conducting gate extending along a third longitudinal axis orthogonal to the first longitudinal axis, the conducting gate disposed above the diffusion region and adjacent to a first side of the dummy gate by a gate pitch;
a circuit comprising:
a Field-Effect Transistor (FET) in the diffusion region, the FET comprising:
a semiconductor channel structure in the diffusion region;
a first gate comprising a first active gate in a portion of the conducting gate disposed above the semiconductor channel structure;
a source in a first end portion of the semiconductor channel structure;
and
a drain in a second end portion of the semiconductor channel structure;
and
a signal output node connected to at least one of the source and the drain of the FET;
an output contact disposed in a first output contact area above the signal output node and in contact with the signal output node;
an output metal interconnect line disposed above the output contact and in contact with the output contact and extending to a second output contact area outside the first output contact area, the second output contact area adjacent to a second side of the dummy gate opposite of the first side of the dummy gate;
a first via disposed above and in contact with the output metal interconnect line in the first output contact area;
and
a second via disposed above and in contact with the output metal interconnect line in the second output contact area.

15 more elements

A integrated circuit (IC), comprising:

a substrate;
a means for providing a diffusion disposed in the substrate, the means for providing the diffusion comprising a means for providing a semiconducting channel;
a means for providing isolation extending above the means for providing the diffusion;
a means for providing a conduction path disposed above the means for providing the diffusion, the means for providing the conduction path adjacent to a first side of the means for providing isolation;
a circuit comprising:
a Field-Effect Transistor (FET) in the means for providing the diffusion, the FET comprising:
a semiconductor channel structure in the means for providing the diffusion;
a first gate comprising a first active gate in a portion of the means for providing a conduction path disposed above the semiconductor channel structure;
a source in a first end portion of the semiconductor channel structure;
and
a drain in a second end portion of the semiconductor channel structure;
and
a signal output node connected to at least one of the source and the drain of the FET;
a means for providing an output contact disposed in a first output contact area above the signal output node and in contact with the signal output node;
a means for interconnecting the means for providing interconnection to the means for providing an output contact disposed above the output contact extending to a second output contact area outside the first output contact area, the second output contact area adjacent to a second side of the means for providing isolation opposite of the first side of the means for providing isolation;
a first means for providing a first vertical interconnect disposed above and in contact with the means for interconnecting the means for providing interconnection to the means for providing the output contact in the first output contact area;
and
a second means for providing a second vertical interconnect disposed above and in contact with the means for interconnecting the means for providing interconnection to the means for providing the output contact in the second output contact area.

15 more elements

A method of fabricating an integrated circuit (IC), comprising:

forming a substrate;
forming a diffusion region in the substrate comprising a semiconductor channel having a first longitudinal axis in a first direction;
forming a dummy gate above the diffusion region and extending along a second longitudinal axis orthogonal to the first longitudinal axis
forming a conducting gate above the diffusion region and adjacent to a first side of the dummy gate by a gate pitch and extending along a third longitudinal axis orthogonal to the first longitudinal axis;
forming a circuit comprising:
a Field-Effect Transistor (FET) in the diffusion region, the FET comprising:
a semiconductor channel structure in the diffusion region;
a first gate comprising a first active gate in a portion of the conducting gate disposed above the semiconductor channel structure;
a source in a first end portion of the semiconductor channel structure;
and
a drain in a second end portion of the semiconductor channel structure;
and
forming a signal output node connected to at least one of the source and the drain of the FET;
forming an output contact disposed in a first output contact area above the signal output node and in contact with the signal output node;
forming an output metal interconnect line disposed above the output contact and in contact with the output contact and extending to a second output contact area outside the first output contact area, the second output contact area adjacent to a second side of the dummy gate opposite of the first side of the dummy gate;
forming a first via disposed above and in contact with the output metal interconnect line in the first output contact area;
and
forming a second via disposed above and in contact with the output metal interconnect line in the second output contact area.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/143,647Filed 27 Sep 2018
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10W 20/498
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: resistive…
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Family

No related US applications are recorded in the indexed filing history.

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