Post-grind die backside power delivery
AssigneeIntel Corporation
InventorsMin-Tih Ted Lai, Tyler Leuten, Florence R. Pon
Life of this patent
Estimating the term…
Abstract
Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
Claims20
A microelectronics package comprising:
- a package substrate;
- and
- a die connected to the package substrate, the die comprising:
- a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;
- a plurality of vias extending through the material layer from the top side to the backside;
- and
- a plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection,
- wherein a first metal channel of the plurality of metal channels is located adjacent a reference channel within the material layer.
A microelectronics package comprising:
- a package substrate;
- and
- a die connected to the package substrate, the die comprising:
- a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;
- a plurality of vias extending through the material layer from the top side to the backside;
- a first metal layer in contact with the backside, the first metal layer in electrical communication with at least one of the plurality of pad connections and a first subset of the plurality of vias;
- and
- a second metal layer located adjacent to the first metal layer and separated by a dielectric, the second metal layer in electrical communication with a second subset of the plurality of vias, the second metal layer being a reference plane,
- wherein the first metal layer is in electrical communication with the power connection.
A memory board, a motherboard, a sound card, or a video card comprising:
- a package substrate;
- and
- a die connected to the package substrate, the die comprising:
- a material layer having a top side and a backside, the top side including a plurality of pad connections and integrated circuitry in electrical communication with the plurality of pad connections, the backside including a power connection;
- a plurality of vias extending through the material layer from the top side to the backside;
- a first metal layer in contact with the backside, the first metal layer in electrical communication with at least one of the plurality of pad connections and a first subset of the plurality of vias;
- and
- a second metal layer located adjacent to the first metal layer and separated by a dielectric, the second metal layer in electrical communication with a second subset of the plurality of vias, the second metal layer being a reference plane,
- wherein the first metal layer is in electrical communication with the power connection.
Dependencies are inferred from the claim text.