Semiconductor package

A semiconductor package comprising:

• a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, the first connection member including an insulating member and a first redistribution layer embedded in the insulating member and having exposed regions in the second surface;
• a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member;
• an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip;
• a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the exposed regions of the first redistribution layer, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias;
• and
• a second connection member having a third surface disposed on the encapsulant and a fourth surface opposing the third surface in the stacking direction, the second connection member including a third redistribution layer connected to the second redistribution layer,
• wherein an area of a surface of at least one of the through-vias adjacent to the first connection member is smaller than an area of a surface of the at least one of the through-vias adjacent to the second connection member.