Transistor device structures with retrograde wells in CMOS applications

A device, comprising:

• a substrate comprising an N-active region and a P-active region;
• a layer of silicon-carbon positioned on and in direct contact with a recessed upper surface of said N-active region;
• a first layer of silicon positioned on said layer of silicon-carbon;
• a second layer of silicon positioned on and in direct contact with a recessed upper surface of said P-active region;
• a layer of a first semiconductor material positioned on said second layer of silicon, said first semiconductor material comprising silicon-germanium, wherein an upper surface of said layer of said first semiconductor material is substantially level with an upper surface of an isolation region defining said P-active region;
• an N-type transistor positioned in and above said N-active region;
• and
• a P-type transistor positioned in and above said P-active region.

A device, comprising:

• a first isolation region positioned in a substrate, said first isolation region defining an N-active region having an upper surface that is recessed relative to an upper surface of said first isolation region;
• a layer of silicon-carbon positioned on and in direct contact with said recessed upper surface of said N-active region;
• a first layer of a first semiconductor material positioned on said layer of silicon-carbon, wherein an upper surface of said first layer of said first semiconductor material is substantially level with said upper surface of said first isolation region;
• a second isolation region positioned in said substrate, said second isolation region defining a P-active region having an upper surface that is recessed relative to an upper surface of said second isolation region;
• a second layer of said first semiconductor material positioned on and in direct contact with said recessed upper surface of said P-active region;
• a layer of a second semiconductor material positioned on said second layer of said first semiconductor material, wherein an upper surface of said layer of said second semiconductor material is substantially level with said upper surface of said second isolation region;
• an N-type transistor positioned in and above said N-active region;
• and
• a P-type transistor positioned in and above said P-active region.