Deep trench isolation structure in semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
Life of this patent
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Abstract
An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.
Claims20
An integrated circuit comprising:
- a semiconductor substrate, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate comprising a handle substrate, a semiconductor layer over the handle substrate, and a buried insulator layer between the handle substrate and the semiconductor layer;
- an isolation region in the semiconductor substrate;
- a first active component on the semiconductor layer of the semiconductor substrate;
- and
- at least one deep trench isolation structure extending from a bottom of the isolation region toward a bottom of the semiconductor substrate, the deep trench isolation structure having at least one air void therein.
An integrated circuit comprising:
- a semiconductor substrate, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate comprising a handle substrate, a semiconductor layer over the handle substrate, and a buried insulator layer between the handle substrate and the semiconductor layer;
- an isolation region in the semiconductor substrate;
- and
- a plurality of deep trench isolation structures extending from a bottom of the isolation region toward a bottom of the semiconductor substrate.
An integrated circuit comprising:
- a semiconductor substrate;
- an isolation region in the semiconductor substrate;
- at least one pillar extending from a bottom of the isolation region toward a bottom of the semiconductor substrate, the pillar tapering in a first direction away from the bottom of the semiconductor substrate;
- and
- a plurality of deep trench isolation structures respectively on opposite sidewalls of the pillar.
Dependencies are inferred from the claim text.