US 10,483,125 B2Granted

Semiconductor device and method for manufacturing same

AssigneeTowerJazz Panasonic Semiconductor Co., Ltd.

InventorsYuka Inoue, Mitsunori Fukura, Nobuyoshi Takahashi, Masahiro Oda, Hisashi Yano, Yutaka Ito, Yasunori Morinaga

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Abstract

A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.

Claims8

Dependent claims

A semiconductor device comprising:

a substrate provided with a first region and a second region;
a first interlayer film formed on an upper surface of the substrate;
a first metal wiring line embedded in an upper portion of the first interlayer film in the first region;
a second interlayer film formed on the first interlayer film and the first metal wiring line;
a second metal wiring line embedded in an upper portion of the second interlayer film in the first region;
a first via penetrating the second interlayer film and electrically connecting the first metal wiring line and the second metal wiring line;
a landing pad embedded in the upper portion of the first interlayer film and penetrating the second interlayer film in the second region;
and
a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad in the second region,
wherein a lower surface position of the landing pad is different from that of the first metal wiring line.

7 more elements

A method for manufacturing a semiconductor device, comprising:

a step of forming a first interlayer film formed on an upper surface of a substrate provided with a first region and a second region and a first metal wiring line embedded in an upper portion of the first interlayer film;
a step of forming a second interlayer film formed on the first interlayer film and the first metal wiring line;
a step of forming, in the first region, a wiring groove in the second interlayer film and a first via hole penetrating the second interlayer film above the first metal wiring line;
a step of forming, in the second region, a pad recessed portion at the upper portion of the first interlayer film and forming a pad hole penetrating the second interlayer film upon formation of the wiring groove and the first via hole;
a step of filling the first via hole, the wiring groove, the pad recessed portion, and the pad hole with metal to form a first via in the first via hole, form a second metal wiring line in the wiring groove, and form a landing pad in the pad recessed portion and the pad hole;
and
a step of forming, in the second region, a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/114,303Filed 28 Aug 2018 · continuation
Priority: 10 Feb 2017
Published: US 2018/0366342 A120 Dec 2018
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10P 14/40
Formation of materials, e.g. in the shape of layers or pillars: of conductive or resistive materials
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0238
The interconnections being through-semiconductor vias: comprising etching via holes through pads or through electrodes

Family

PCT/JP2017/004961Parent of this continuation · filed 10 Feb 2017
US 2018/0366342 A1Pre-grant publication · published 20 Dec 2018
US 10,483,125 B2This patent

From the US filing history. Foreign family members aren’t listed.

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