Embedded memory in back-end-of-line low-k dielectric

A device comprising:

• a substrate comprising circuit components disposed on a substrate surface;
• a plurality of interlevel dielectric (ILD) levels disposed on the substrate over the circuit components, wherein the plurality of interlevel dielectric (ILD) levels include a cell dielectric layer;
• a storage unit of a memory cell between two adjacent ILD layers, wherein the storage unit is formed in the cell dielectric layer, the cell dielectric layer is disposed between the two adjacent ILD layers, the cell dielectric layer comprises a low-k dielectric material and is disposed over the storage unit;
• and
• a polishing rate enhancer layer over the cell dielectric layer, the polishing rate enhancer layer comprising an oxide layer.