Hybrid double patterning method for semiconductor manufacture

A method of fabricating an integrated circuit (IC) with a first lithography technique and a second lithography technique having a lower resolution than the first lithography technique, comprising:

• providing a layout of the IC, the layout having a set of IC patterns;
• deriving a graph from the layout by representing the IC patterns with vertices and representing spacing between IC patterns with edges connecting the corresponding vertices;
• classifying the edges into two types, a first type of edges representing spacing that cannot be resolved by the first lithography technique, a second type of edges representing spacing that cannot be resolved by the second lithography technique but can be resolved by the first lithography technique;
• and
• checking if there is a loop formed by odd number of vertices connected by edges of the first type.

A method of fabricating an integrated circuit (IC) with a first lithography technique having a first resolution and a second lithography technique having a second resolution, the first resolution being finer than the second resolution, comprising:

• receiving a layout of the IC, the layout having IC patterns;
• deriving a graph from the layout, the graph having vertices and edges that connect some of the vertices, the vertices representing the IC patterns, the edges representing spacing between the IC patterns that are smaller than the second resolution;
• classifying the edges into at least two types, a first type representing spacing that is smaller than the first resolution, a second type representing spacing that is equal to or greater than the first resolution but smaller than the second resolution;
• and
• assigning two colors to all vertices that are connected by edges of the first type, wherein two vertices connected by a common edge of the first type are assigned with different colors.