Semiconductor device and method of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
Life of this patent
Estimating the term…
Abstract
A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- patterning a middle layer and a bottom layer to expose a spacer material located over a hard mask, wherein prior to the patterning the middle layer and the bottom layer are located on a first side of the spacer layer and a semiconductor substrate is located on a second side of the spacer layer opposite the first side;
- and
- applying an etchant to be in physical contact with both the middle layer and the spacer material, wherein the etchant comprises an inhibitor which inhibits an etch rate of the spacer material.
A method of manufacturing a semiconductor device, the method comprising:
- depositing a spacer material over and along sidewalls of a mandrel;
- placing a tri-layer photoresist over the spacer material, the tri-layer photoresist comprising:
- a bottom layer;
- a middle layer;
- and
- a photoresist;
- patterning the middle layer and the bottom layer to form a first opening and expose the spacer material;
- removing the middle layer with an etching solution, the etching solution comprising an inhibitor to lower an etch rate of the spacer material during the removing the middle layer;
- and
- filling the first opening with a masking material, wherein the filling the first opening comprises filling the first opening with a dielectric material.
A method of manufacturing a semiconductor device, the method comprising:
- patterning a middle layer and a bottom layer to expose a layer of titanium oxide, wherein prior to the patterning the middle layer and the bottom layer are located on an opposite side of the layer of titanium oxide from a semiconductor substrate;
- applying an etchant to remove the middle layer;
- and
- lowering an etching rate of the layer of titanium oxide by simultaneously applying an inhibitor to the layer of titanium oxide, wherein the inhibitor comprises an N-ethanolamide derivative ligand.
Dependencies are inferred from the claim text.