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US 10,482,990 B2Granted
Memory device and memory system
AssigneeToshiba Memory Corporation
InventorKatsuhiko Hoya
Life of this patent
Estimating the term…
Abstract
A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.
Claims19
A memory device comprising:
- memory elements which store data and parity;
- a first decoder which, when a first operation including checking of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of a first number of bits in a unit of the data;
- and
- a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of a second number of bits in a unit of the data,
- wherein the second number of bits is smaller than the first number of bits,
- wherein in response to a first command, the memory device:
- reads the data and the parity from the memory elements,
- generates the syndrome from the data and the parity, and
- uses the syndrome to correct the error of the data, and
- wherein in response to a read command, the memory device:
- reads the data and the parity from the memory elements,
- generates the syndrome from the data and the parity,
- uses the syndrome to correct the error of the data, and
- transmits the data in which the error has been corrected.
11 more elements
A memory system comprising:
- a memory device including memory elements which store data and parity;
- a memory controller which controls the memory device;
- and
- a host device which controls the memory controller,
- wherein during a first operation including checking of the data, the memory controller:
- transmits a first command to the memory device to read the data and the parity from the memory elements while no external access is being made to the memory device,
- generates a syndrome from the data and the parity, and
- uses the syndrome to correct an error of a maximum of a first number of bits in a unit of the data,
- wherein during reading of the data, the memory controller:
- transmits a read command to the memory device, and reads the data and the parity from the memory elements,
- generates a syndrome from the data and the parity, and
- uses the syndrome to correct an error of a maximum of a second number of bits in a unit of the data, and
- wherein the second number of bits is smaller than the first number of bits.
10 more elements
A memory system comprising:
- a memory device including memory elements which store data and parity;
- a memory controller which controls the memory device;
- and
- a host device which controls the memory controller,
- wherein:
- during a first operation, the memory controller transmits a first command to the memory device while no external access is being made to the memory device,
- in response to the first command, the memory device reads the data and the parity from the memory elements, generates a syndrome from the data and the parity, and transmits the syndrome to the memory controller,
- upon receipt of the syndrome, the memory controller uses the syndrome to correct an error of a maximum of a first number of bits in a unit of the data,
- during reading of the data, the memory controller transmits a read command to the memory device,
- in response to the read command, the memory device reads the data and the parity from the memory elements, generates a syndrome from the data and the parity, uses the syndrome to correct an error of a maximum of a second number of bits in a unit of the data, and transmits the data in which the error has been corrected to the memory controller, and
- wherein the second number of bits is smaller than the first number of bits.
8 more elements
Dependencies are inferred from the claim text.