US 10,482,986 B2 · Adaptive erase fail bit criteria

Abstract

Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Claims20

Dependent claims

An apparatus, comprising:

a group of non-volatile memory cells;
an erase circuit configured to perform an erase operation on the group;
a counting circuit configured to determine whether a first fail bit count for the group with respect to a first erase verify level for the erase operation exceeds an allowed fail bit count;
the counting circuit further configured to determine a second fail bit count for the group with respect to a second erase verify level that is a higher magnitude reference voltage than the first erase verify level responsive to the first fail bit count being above the allowed fail bit count;
and
a response circuit configured to increase the allowed fail bit count for the erase verify level to at least the second fail bit count responsive to the second fail bit count being between a first number and a second number.

3 more elements

A non-volatile storage device, comprising:

a group of NAND strings of non-volatile memory cells;
erase means for performing an erase operation on the group of NAND strings;
counting means for determining whether more than an allowed number of NAND strings in the group have at least one memory cell with a threshold voltage greater than a first erase verify reference voltage after the erase operation;
the counting means further for determining a count of NAND strings in the group that have at least one memory cell with a threshold voltage greater than a second erase verify reference voltage that is greater than the first erase verify reference voltage responsive to more than the allowed number of NAND strings in the group having at least one memory cell having a threshold voltage greater than the first erase verify reference voltage after the erase operation;
and
response means for increasing the number of NAND strings that are allowed to have at least one memory cell having a threshold voltage above the first erase verify reference voltage and still pass the erase operation to at least the count responsive to determining the count is between a first number and a second number.

3 more elements

Dependencies are inferred from the claim text.

Adaptive erase fail bit criteria

Life of this patent

Adaptive erase fail bit criteria

Life of this patent

Abstract

Claims20