US 10,482,979 B1 · Capacitive voltage modifier for power management

Abstract

A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

Claims24

Dependent claims

A memory sub-system, comprising:

a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system, the PMIC configured to output a plurality of voltages for operation of the memory sub-system based on a PMIC supply voltage;
and
a capacitive voltage modifier (CVM) coupled to the PMIC, the CVM configured to:
receive the primary supply voltage of the memory sub-system as an input;
and
provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, wherein the first MPSV is not higher than the uppermost PMIC supply voltage.

3 more elements

Dependencies are inferred from the claim text.

Capacitive voltage modifier for power management

Life of this patent

Capacitive voltage modifier for power management

Life of this patent

Abstract

Claims24