Read voltage optimization method, memory storage device and memory control circuit unit

A storage controller, controlling a storage device comprising a rewritable non-volatile memory module, the storage controller comprising:

• a connection interface circuit, coupled to a host system;
• a memory interface control circuit, coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of word lines, each of the word lines comprises a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different Gray codes, a total number of the Gray codes is N, and N is a first predetermined positive integer greater than 2;
• a read voltage management circuit unit;
• and
• a processor, coupled to the connection interface circuit, the memory interface control circuit, and the read voltage management circuit unit,
• wherein the processor chooses a target word line of the word lines, instructs the read voltage management circuit unit to perform a read voltage optimization operation corresponding to the target word line, a plurality of target memory cells of the target word line are programmed, and wherein in the read voltage optimization operation:
• the read voltage management circuit unit respectively reads the target memory cells by using different X read voltage sets to obtain corresponding X Gray code summation sets, wherein X is a second predetermined positive integer, the X read voltage sets and the corresponding X Gray code summation sets are arranged based on a first predetermined order, a voltage difference between every pair of adjacent read voltage sets in the X read voltage sets is a predetermined voltage difference, each of the X read voltage sets has N−1 read voltages arranged based on a second predetermined order, wherein each of the X Gray code summation sets has N−1 Gray code count summations arranged based on the second predetermined order, and a jth Gray code count summation in the N−1 Gray code count summations corresponds to a jth read voltage in the N−1 read voltages, wherein the jth Gray code count summation is calculated by summing up first j Gray code counts among N Gray code counts, wherein the N Gray code counts are calculated by summing up the numbers of a plurality of read bit values classified into the respective Gray codes, wherein the read bit values are obtained by using a corresponding read voltage set to read the target memory cells,
• wherein the read voltage management circuit unit further chooses every pair of adjacent Gray code summation sets in the X gray code summation sets based on the first predetermined order and calculates a Gray code count summation difference of the Gray code count summations at the same sequence position in the respective N−1 Gray code count summations between every chosen pair of two Gray code summation sets based on the second predetermined order to obtain X−1 Gray code count summation difference sets corresponding to all the chosen pairs of the Gray code summation sets, wherein each of the X−1 Gray code count summation difference sets comprises N−1 Gray code count summation differences arranged based on the second predetermined order, and a jth Gray code count summation difference in the N−1 Gray code count summation differences corresponds to the jth read voltage in the N−1 read voltages, and
• wherein the read voltage management circuit unit further determines N−1 optimized read voltages corresponding to the second predetermined order from X*(N−1) read voltages belonging to the X read voltage sets based on the N−1 Gray code count summation differences of each of the X−1 Gray code count summation difference sets to form an optimized read voltage set corresponding to the target word line and complete the read voltage optimization operation corresponding to the target word line.