Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array;
• an interface circuit through which commands to read from and write to the memory cell array are to be received;
• a power supply protection circuit connected to the interface circuit to supply voltages to the interface circuit;
• a first pad through which a first voltage is supplied to the power supply protection circuit;
• and
• a second pad through which a second voltage different from the first voltage is supplied to the power supply protection circuit, wherein
• the power supply protection circuit includes:
• a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node,
• a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node,
• a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor,
• a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and
• a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node.

A method of protecting a semiconductor memory device against a voltage surge at a first pad by turning on a power supply protection transistor connected between the first pad and a second pad, the power supply protection transistor being turned off when there is no voltage surge at the first pad, said method comprising:

• in response to a voltage at the first pad exceeding a threshold voltage, pulling up a gate voltage of the power supply protection transistor to turn on the power supply protection transistor and cause a current to flow from the first pad to the second pad;
• and
• in response to the voltage at the first pad not exceeding the threshold voltage, pulling down the gate voltage of the power supply protection transistor to turn off the power supply protection transistor and stop any current from flowing from the first pad to the second pad, wherein
• the gate voltage of the power supply protection transistor is equal to a voltage at a first node of the semiconductor memory device, and
• the semiconductor memory device includes:
• a first transistor including a first end electrically connected to the first pad and a second end electrically connected to the first node,
• a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node,
• a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor,
• a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and
• a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node.