Operation of a memory device during programming

A method of operating a memory, comprising:

• applying a first voltage level to a first data line and to a second data line while applying a second voltage level, lower than the first voltage level, to a first select gate connected between the first data line and a first string of series-connected memory cells and to a second select gate connected between the second data line and a second string of series-connected memory cells;
• applying a third voltage level, lower than the first voltage level, to the first data line while continuing to apply the first voltage level to the second data line and while continuing to apply the second voltage level to the first select gate and to the second select gate;
• applying a fourth voltage level, higher than the third voltage level, to the first select gate while continuing to apply the second voltage level to the second select gate;
• applying a fifth voltage level, higher than the first voltage level, to a first access line and to a second access line while continuing to apply the fourth voltage level to the first select gate and while continuing to apply the second voltage level to the second select gate;
• and
• applying a sixth voltage level, higher than the fifth voltage level, to the first access line while continuing to apply the fifth voltage level to the second access line.

A method of operating a memory, comprising:

• applying a first voltage level to each data line of a plurality of data lines while applying a second voltage level, lower than the first voltage level, to each select gate of a plurality of select gates each connected between a respective data line of the plurality of data lines and a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells;
• applying a third voltage level, lower than the first voltage level, to a particular data line of the plurality of data lines while continuing to apply the first voltage level to a different data line of the plurality of data lines and while continuing to apply a voltage level lower than the first voltage level to each select gate of the plurality of select gates;
• applying a fourth voltage level, higher than the third voltage level, to a particular select gate of the plurality of select gates connected between the particular data line and a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells while continuing to apply a voltage level lower than the first voltage level to a different select gate of the plurality of select gates connected between the different data line and a different string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• applying a fifth voltage level, higher than the first voltage level, to each access line of a plurality of access lines while continuing to apply a voltage level higher than the third voltage level to the particular select gate and while continuing to apply a voltage level lower than the first voltage level to the different select gate;
• and
• applying a sixth voltage level, higher than the fifth voltage level, to a particular access line of the plurality of access lines while continuing to apply the fifth voltage level to a different access line of the plurality of access lines.