Memory devices including a word line defect detection circuit

A memory device comprising:

• a memory cell array comprising a memory cell and a word line that is connected to the memory cell;
• a voltage generator configured to receive a power supply voltage, generate a pumping clock signal, and provide an operating voltage to the word line to program the memory cell;
• a compensation circuit configured to provide a compensated reference clock signal that compensates for variations in the power supply voltage and;
• and
• a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing a first number of pulses included in the pumping clock signal and a second number of pulses included in the compensated reference clock signal.

A memory device comprising:

• a voltage generator configured to receive a power supply voltage, to generate an operating voltage using the power supply voltage, and to generate a pumping clock signal;
• a compensation circuit configured to provide a compensated reference clock signal that compensates for variations in the power supply voltage;
• a pass/fail (P/F) determining circuit configured to perform a comparison of a first number of pulses of the pumping clock signal and a second number of pulses of the compensated reference clock signal and to generate a pass/fail signal responsive to the comparison;
• and
• a controller configured to control operation of the memory device responsive to the pass/fail signal.