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US 10,482,972 B2Granted
Memory as a programmable logic device
AssigneeMicron Technology, Inc.
InventorsLuca De Santis, Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.
Claims20
A memory, comprising:
- a data line;
- a plurality of strings of series-connected memory cells selectively connected to the data line;
- a plurality of first access lines, wherein, for each first access line of the plurality of first access lines, that first access line is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a plurality of second access lines, wherein, for each second access line of the plurality of second access lines, that second access line is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.
2 more elements
A memory, comprising:
- a data line;
- a plurality of strings of series-connected memory cells selectively connected to the data line;
- sense circuitry selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells through the data line;
- a plurality of first access lines, wherein, for each first access line of the plurality of first access lines, that first access line is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a plurality of second access lines, wherein, for each second access line of the plurality of second access lines, that second access line is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises a plurality of memory cell pairs;
- and
- wherein the memory is configured to program each memory cell pair of the plurality of memory cell pairs to complementary data states when programming the memory cells of the plurality of strings of series-connected memory cells.
6 more elements
A memory, comprising:
- a data line;
- a plurality of strings of series-connected memory cells selectively connected to the data line;
- sense circuitry selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells through the data line;
- a plurality of first access lines having a plurality of first access line pairs, wherein, for each first access line of the plurality of first access lines, that first access line is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a plurality of second access lines, wherein, for each second access line of the plurality of second access lines, that second access line is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- wherein the memory is configured to program each memory cell having a control gate coupled to a first access line of the plurality of first access lines to one of two data states when programming the memory cells of the plurality of strings of series-connected memory cells;
- wherein, for each first access line pair of the plurality of first access line pairs, the memory is configured to apply a first voltage level to one first access line of that first access line pair and to apply a second voltage level to the other first access line of that first access line pair when determining a function result of the plurality of strings of series-connected memory cells;
- wherein the first voltage level applied to a first access line of the plurality of first access lines is configured to activate a memory cell having a control gate coupled to that first access line and having a first data state of the two data states, and to deactivate a memory cell having a control gate coupled to that first access line and having a second data state of the two data states;
- and
- wherein the second voltage level applied to a first access line of the plurality of first access lines is configured to activate a memory cell having a control gate coupled to that first access line and having the first data state, and to activate a memory cell having a control gate coupled to that first access line and having the second data state.
8 more elements
Dependencies are inferred from the claim text.