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US 10,482,971 B2Granted
Semiconductor memory apparatus and operating method of the semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorsJin Su Park, Taek Seung Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.
Claims27
A semiconductor memory apparatus comprising:
- a memory cell;
- and
- a current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, perform a reset write operation without limiting a voltage level across the memory cell, and limit the voltage level across the memory cell to a level of a clamping voltage in a set write operation.
A semiconductor memory apparatus comprising:
- a memory cell;
- and
- a current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, and selectively limit a voltage level across the memory cell to a level of a clamping voltage based on whether the write operation is a set write operation or a reset write operation.
A method for operating a semiconductor memory apparatus, comprising:
- determining a resistance state of a memory cell by performing a pre-read operation when a set write operation or a reset write operation is started;
- and
- selectively limiting a voltage across a memory cell to a level of a clamping voltage based on whether it is a set write operation or a reset write operation.
A semiconductor memory apparatus comprising:
- a memory cell;
- and
- a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell prior to changing the resistance state of the memory cell.
Dependencies are inferred from the claim text.