Block decoder of nonvolatile memory and level shifter

A block decoder of nonvolatile memory, comprising:

• a level shifter, comprising:
• a first transistor, wherein the first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage;
• a second transistor, wherein the second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node;
• a third transistor, wherein the third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to a second supply voltage;
• and
• a fourth transistor, wherein the fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node;
• and
• a decoder, coupled to a third supply voltage, wherein the decoder outputs a first control voltage to the first control node and outputs a second control voltage to the second control node.