Electronic device with a reference resistance adjustment block

An electronic device including a semiconductor memory, the semiconductor memory comprising:

• a plurality of bit lines and a plurality of source lines;
• a plurality of resistive storage cells coupled between a corresponding bit line and a corresponding source line among the plurality of bit lines and the plurality of source lines;
• a plurality of reference bit lines and a plurality of reference source lines;
• a plurality of reference resistance blocks coupled between a corresponding reference bit line and a corresponding reference source line among the plurality of reference bit lines and the plurality of reference source lines, and each including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series;
• a plurality of data sensing blocks each comparing a read current flowing through a corresponding bit line among the plurality of bit lines and a reference current flowing through a corresponding reference bit line among the plurality of reference bit lines to determine data stored in a resistive storage cell selected among a plurality of resistive storage cells coupled to the corresponding bit line;
• and
• a reference resistance adjustment block coupled to the reference resistance blocks and structured to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust resistance values of the reference resistance blocks, and
• wherein a bias voltage having a fixed voltage level is supplied to the first reference resistance transistor as the first gate voltage during an operation to determine data stored in the selected resistive storage cell and an adjustment voltage having a varying voltage level adjusted depending on a temperature is supplied to the second reference resistance transistor as the second gate voltage.