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US 10,482,957 B2Granted
Resistive RAM memory cell
AssigneeSTMicroelectronics (Rousset) SAS
InventorsPhilippe Boivin, Simon Jeannot, Olivier Weber
Life of this patent
Estimating the term…
Abstract
The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
Claims18
A memory cell comprising:
- a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in a substrate layer;
- and
- a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the memory element rests at least partially on a top surface of the gate of the selection transistor.
A memory, comprising:
- a substrate layer;
- and
- first and second memory cells each including:
- a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer;
- and
- a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side, wherein in each of the first and second memory cells, the memory element of the memory cell rests at least partially on a top surface of the gate of the selection transistor of the memory cell.
3 more elements
A memory, comprising:
- a silicon on insulator substrate that includes a semiconductor layer on a buried insulating layer;
- first and second memory cells each including:
- a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer;
- and
- a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side;
- and
- an insulating region extending between the conductive zone of the first memory cell and the conductive zone of the second memory cell, the insulating region including a portion of the buried insulating layer.
4 more elements
Dependencies are inferred from the claim text.