Multi-state memory device and method for adjusting memory state characteristics of the same

Abstract

A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

Dependencies are inferred from the claim text.