Systems and methods for improved error correction in a refreshable memory

A computer system for implementing error correction control (ECC), the system comprising:

• a refreshable memory device, the memory device comprising a parity region and a user data region, the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
• a system on a chip (SoC) in communication with the memory device;
• and
• logic of the SoC configured to:
• determine a first refresh rate for the user data region of the memory device;
• determine a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of:
• a ratio to the first refresh rate, and calibration data;
• generate parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
• refresh the user data region of the memory device at the first refresh rate;
• refresh the parity region of the memory device at the second refresh rate;
• and
• determining that a change in the second refresh rate for the parity region is needed based on at least one of:
• a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for implementing error correction control (ECC) on a computing device, the method comprising:

• defining a parity region and a user data region of a refreshable memory device, the memory device coupled to a system on a chip (SoC), the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
• determining with the SoC a first refresh rate for the user data region of the memory device;
• determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of:
• a ratio to the first refresh rate, and calibration data;
• generating parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
• refreshing the user data region of the memory device at the first refresh rate;
• refreshing the parity region of the memory device at the second refresh rate;
• and
• determining that a change in the second refresh rate for the parity region is needed based on at least one of:
• a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

A computer system for implementing error correction control (ECC) on a computing device, the system comprising:

• means for defining a parity region and a user data region of a refreshable memory device, the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits, the memory device coupled to a system on a chip (SoC);
• means for determining with the SoC a first refresh rate for the user data region of the memory device;
• means for determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of:
• a ratio to the first refresh rate, and calibration data;
• means for generating parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
• means for refreshing the user data region of the memory device at the first refresh rate;
• means for refreshing the parity region of the memory device at the second refresh rate;
• and
• means for determining that a change in the second refresh rate for the parity region is needed based on at least one of:
• a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.