Memory devices and memory systems including the same

A memory system, comprising:

• a memory controller configured to output
• a data signal including a plurality of pieces of data, the plurality of pieces of data including at least one piece of dummy data preceding a plurality of pieces of effective data, and
• a strobe signal including a plurality of timing pulses;
• and
• a memory device including
• a strobe buffer configured to receive the strobe signal,
• a phase detection unit configured to detect a phase difference between the data signal and the strobe signal output from the strobe buffer based on the at least one piece of dummy data and the strobe signal,
• a phase adjust unit configured to adjust a phase of the strobe signal output from the strobe buffer according to the phase difference, and
• a sampling unit configured to sample the data signal according to the strobe signal output from the phase adjust unit.

A memory system, comprising:

• a memory controller configured to output a plurality of data signals and a strobe signal corresponding to the plurality of data signals, each of the plurality of data signals including effective data, the effective data being delayed for a determined duration with respect to the strobe signal;
• and
• a memory device configured to
• receive the strobe signal via a strobe buffer,
• replicate the strobe signal to generate a plurality of strobe signals, a quantity of strobe signals in the plurality of strobe signals corresponding to a quantity of data signals in the plurality of data signals,
• adjust a phase of each of the plurality of strobe signals based on the plurality of data signals and the plurality of strobe signals, and
• sample the plurality of data signals according to respective strobe signals of the plurality of strobe signals.