Memory controller architecture with improved memory scheduling efficiency

An integrated circuit comprising:

• field programmable gate array (FPGA) circuitry configured to be programmed to implement user logic;
• user interface circuitry configured to couple to the user logic of the FPGA circuitry to receive memory commands from the user logic of the FPGA circuitry;
• physical layer circuitry configured to couple to a memory and configured to access the memory in response to the memory commands;
• and
• a memory controller circuit, configured to couple between the physical layer circuitry and the user interface circuitry, wherein the memory controller circuit comprises:
• a plurality of column address arbiters configured to arbitrate between read and write memory access requests;
• a plurality of finite state machine circuits configured to operate in parallel to queue the memory commands from the user interface circuitry for accessing the memory, wherein the plurality of finite state machine circuits are each configured to receive one or more of the memory commands for queuing;
• a logic circuit configured to order the memory commands for accessing the memory;
• and
• a final arbiter circuit configured to select a respective memory command of the memory commands from the user interface circuitry to issue to the physical layer circuitry, wherein the plurality of finite state machine circuits operate based at least in part on a feedback signal associated with arbitration results of the final arbiter circuit.

A system, comprising:

• field programmable gate array (FPGA) circuitry disposed on an integrated circuit, wherein the FPGA circuitry is configured to be programmed to implement user logic;
• a processor configured to receive and process data from the FPGA circuitry;
• user interface circuitry configured to couple to the user logic of the FPGA circuitry to receive memory commands from the user logic of the FPGA circuitry;
• physical layer circuitry configured to couple to a memory and configured to access the memory in response to the memory commands;
• and
• a memory controller circuit, configured to couple between the physical layer circuitry and the user interface circuitry, having:
• a plurality of column address arbiters configured to arbitrate between read and write memory access requests;
• a plurality of finite state machine circuits configured to operate in parallel to queue the memory commands from the user interface circuitry for accessing the memory, wherein the plurality of finite state machine circuits are each configured to receive one or more of the memory commands for queuing;
• and
• one or more logic circuits configured to order the memory commands for accessing the memory prior to the memory commands issuing to the physical layer circuitry, wherein the plurality of finite state machine circuits operate based at least in part on a feedback signal associated with a command issued to the physical layer.