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US 10,482,931 B1Granted
Reversed bias compensation for sense amplifier operation
AssigneeMicron Technology, Inc.
InventorShinichi Miyatake
Life of this patent
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Abstract
Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.
Claims26
An apparatus comprising:
- first and second signal lines;
- a first transistor coupled between the first signal line and a first common source line, wherein a first gate of the first transistor is coupled to a biasing circuit;
- and
- a second transistor coupled to the second signal line and the first common source line, wherein a second gate of the second transistor is coupled to the biasing circuit;
- wherein the biasing circuit is configured to:
- couple to the first gate of the first transistor to the second signal line and the second gate of the second transistor to the first signal line in a first configuration;
- and
- couple the first gate of the first transistor and the second gate of the second transistor to a first voltage line in a second configuration.
5 more elements
A memory device, comprising:
- a first plurality of memory cells and a second plurality of memory cells;
- and
- a sense amplify circuit coupled to the first plurality of memory cells through a first data line and coupled to the second plurality of memory cells through a second data line, wherein the sense amplify circuit comprises a biasing circuit and a flip-flop, wherein the flip-flop comprises:
- a first transistor coupled between the first data line and a first common source line, wherein a first gate of the first transistor is coupled to a first output of the biasing circuit;
- and
- a second transistor coupled between the second data line and the first common source line, wherein a second gate of the second transistor is coupled to a second output of the biasing circuit;
- and
- wherein the biasing circuit is configured to:
- couple the second data line to the first output of the biasing circuit and couple the first data line to the second output of the biasing circuit during a readout phase;
- and
- couple a first voltage line to the first output of the biasing circuit and couple the first voltage line to the second output of the biasing circuit during a compensation phase.
8 more elements
A memory device comprising:
- first and second data lines, wherein the first data line is coupled to a memory cell;
- a flip-flop comprising:
- a first transistor comprising a first source terminal coupled to the first data line, a first gate terminal coupled to a first output of a biasing circuit and a first drain terminal coupled to a first common source line;
- and
- a second transistor comprising a second source terminal coupled to the second data line, a second gate terminal coupled to a second output of the biasing circuit and a second drain terminal coupled to the first common source line;
- and
- reversed bias compensation circuitry comprising the biasing circuit, a pre-charge circuitry, wherein the reversed bias compensation circuitry is configured to:
- pre-charge and equalize the first data line and the second data line to a pre-charge voltage using the pre-charge circuitry;
- during a compensation phase, connect the first gate terminal and the second gate terminal to a first voltage higher than the pre-charge voltage using the biasing circuit;
- and
- during a readout phase, connect the first gate terminal to the second data line and the second gate terminal to the first data line and connect the memory cell to the first data line;
- and
- wherein the compensation phase is configured to generate a first voltage difference between the first data line and the second data line that is proportional to a difference ΔVth between a first gate-source threshold voltage of the first transistor and a second gate-source threshold voltage of the second transistor.
10 more elements
A memory device comprising a sense amplifier configured to sense a voltage difference between first and second signal lines, wherein the sense amplifier comprises:
- a first transistor coupled between the first signal line and a first power node, the first transistor having a first gate coupled to a first circuit node;
- a second transistor coupled between the second signal line and the first power node, the second transistor having a second gate coupled to a second circuit node;
- a third transistor coupled between the second signal line and the first circuit node, the third transistor having a third gate coupled to a first control node;
- a fourth transistor coupled between the first signal line and the second circuit node, the fourth transistor having a fourth gate coupled to the first control node;
- a fifth transistor coupled between the first circuit node and a second power node, the fifth transistor having a fifth gate coupled to a second control node;
- and
- a sixth transistor coupled between the second circuit node and the second power node, the sixth transistor having a sixth gate coupled to the second control node.
4 more elements
Dependencies are inferred from the claim text.