Back to results
US 10,482,930 B2Granted
Memory chip with reduced power consumption, buffer chip module controlling the same and memory module including the same
AssigneeSK hynix Inc.
InventorYoung-Suk Moon
Life of this patent
Estimating the term…
Abstract
In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.
Claims17
A memory chip, comprising:
- a chip select (CS) buffer configured to receive a chip select signal;
- a chip identification (CID) buffer configured to receive a chip identification signal;
- and
- a command (CMD) buffer configured to receive a command signal,
- wherein the chip identification signal is input after a time has elapsed since the chip select signal is activated and before the command signal is input and the CID buffer is activated when the chip identification signal is input, and
- wherein the command signal is input after a time has elapsed since the identification signal is input and the CMD buffer is activated when the command signal is input.
3 more elements
A buffer chip module, comprising:
- a control signal queue configured to receive a control signal divided into a chip select signal, a chip identification signal, a command signal, and an address signal, and to store the chip select signal, the command signal, and the address signal;
- and
- an arbiter configured to output the divided control signal stored in the control signal queue according to a predetermined timing condition,
- wherein the arbiter outputs the chip identification signal before outputting the command signal and after the chip select signal is activated.
1 more element
A memory module, comprising:
- a plurality of memory chips each including a chip select (CS) buffer buffering a chip select signal, a chip identification (CID) buffer buffering a chip identification signal, a command (CMD) buffer buffering a command signal and an address (ADDR) buffer buffering an address signal;
- and
- a buffer chip module configured to output the chip select signal, the chip identification signal, the command signal, and the address signal to the plurality of memory chips,
- wherein the buffer chip module outputs the chip identification signal before outputting the command signal and after a predetermined time has elapsed since the chip select signal is activated, and a CMD buffer and an ADDR buffer, included in a memory chip among the plurality of memory chips, are de-activated before the chip select signal is activated and before the chip identification signal is output.
1 more element
Dependencies are inferred from the claim text.