US 10,482,929 B2Granted

Non-volative (NV) memory (NVM) matrix circuits employing NVM matrix circuits for performing matrix computations

AssigneeQUALCOMM Incorporated

InventorsXia Li, Bin Yang, Gengming Tao

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Abstract

Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

Claims29

Dependent claims

A non-volatile (NV) memory (NVM) matrix circuit, comprising:

a plurality of word lines configured to receive an input vector represented by an input voltage on each word line among the plurality of word lines;
a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;
a plurality of source lines;
a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of NVM bit cell circuits;
each NVM bit cell circuit among the plurality of NVM bit cell circuits having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;
each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit, comprising:
a gate node coupled to a corresponding word line among the plurality of word lines;
and
each NVM bit cell circuit configured to couple its resistance to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node;
and
a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line;
each access transistor among the plurality of access transistors comprising an access gate node coupled to an access line;
and
each access transistor among the plurality of access transistors configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in response to an access voltage applied to the access gate node;
wherein an NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line among the plurality of source lines coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits.

12 more elements

A method of performing matrix multiplication in a non-volatile (NV) memory (NVM) matrix circuit, comprising:

applying a line voltage on at least one bit line among a plurality of bit lines coupled to a corresponding NVM storage string circuit among a plurality of NVM storage string circuits, to electrically couple the line voltage to the corresponding NVM storage string circuit coupled to a corresponding bit line among the plurality of bit lines, each NVM storage string circuit among the plurality of NVM storage string circuits comprising a plurality of NVM bit cell circuits each having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;
applying a second line voltage on at least one source line among a plurality of source lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits, to electrically couple the second line voltage to the corresponding NVM storage string circuit coupled to a corresponding source line among the plurality of source lines;
applying a plurality of input voltages representing an input vector on a plurality of word lines, each word line among the plurality of word lines coupled to a corresponding gate node of an NVM bit cell circuit in each of the plurality of NVM storage string circuits, to electrically couple the NVM bit cell circuit to the source line to couple the resistance of the NVM bit cell circuit to the source line;
and
applying an access voltage to a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line, to electrically couple the corresponding bit line to the corresponding NVM storage string circuit.

2 more elements

A non-volatile (NV) memory (NVM) matrix system, comprising:

a first NVM matrix circuit, comprising:
a plurality of first word lines configured to receive a first input vector represented by a first input voltage on each first word line among the plurality of first word lines;
a plurality of first bit lines, each first bit line among the plurality of first bit lines configured to receive a corresponding first line voltage;
a plurality of first source lines each coupled to a first output node among a plurality of first output nodes;
a plurality of first NVM storage string circuits, each first NVM storage string circuit among the plurality of first NVM storage string circuits configured to be electrically coupled between a corresponding first bit line among the plurality of first bit lines and a corresponding first source line among the plurality of first source lines, each comprising a plurality of first NVM bit cell circuits;
each first NVM bit cell circuit among the plurality of first NVM bit cell circuits having a resistance representing a stored memory state in the first NVM bit cell circuit to form a first data vector for the corresponding first NVM storage string circuit;
and
each first NVM bit cell circuit among the plurality of first NVM bit cell circuits in the first NVM storage string circuit comprising:
a first gate node coupled to a corresponding first word line among the plurality of first word lines;
and
each first NVM bit cell circuit configured to couple its resistance to the first source line in response to the first input voltage applied to the corresponding first word line coupled to the first gate node;
and
a second NVM matrix circuit, comprising:
a plurality of second word lines each coupled to an output node among the plurality of first output nodes;
a plurality of second bit lines, each second bit line among the plurality of second bit lines configured to receive a corresponding second line voltage;
a plurality of second source lines each coupled to a second output node among a plurality of second output nodes;
and
a plurality of second NVM storage string circuits, each second NVM storage string circuit among the plurality of second NVM storage string circuits configured to be electrically coupled between a corresponding second bit line among the plurality of second bit lines and a corresponding second source line among the plurality of second source lines, each comprising a plurality of second NVM bit cell circuits;
each second NVM bit cell circuit among the plurality of second NVM bit cell circuits having a resistance representing a stored memory state in the second NVM bit cell circuit to form a second data vector for the corresponding second NVM storage string circuit;
and
each second NVM bit cell circuit among the plurality of second NVM bit cell circuits in the second NVM storage string circuit comprising:
a second gate node coupled to a corresponding second word line among the plurality of second word lines;
and
each second NVM bit cell circuit configured to couple its resistance to the second source line in response to a second input voltage applied to the corresponding second word line coupled to the second gate node.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/817,441Filed 20 Nov 2017 · us provisional application
Priority: 13 Jul 2017
Published: US 2019/0019538 A117 Jan 2019
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

G11C 5/02
Details of stores covered by group G11C11/00: disposition of storage elements, e.g. in the form of a matrix array
G06N 3/0464
Architecture, e.g. interconnection topology: convolutional networks [CNN, ConvNet]
G06N 3/049
Architecture, e.g. interconnection topology: temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
G06N 3/065
Using electronic means: analogue means

Family

Application62/531,921Us provisional application · filed 13 Jul 2017
US 2019/0019538 A1Pre-grant publication · published 17 Jan 2019
US 10,482,929 B2This patent

From the US filing history. Foreign family members aren’t listed.

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